The present invention relates to semiconductor devices and, in particular, to structures and methods for closing exposed pores in a patterned low-k dielectric prior to metallization.
Because of continuing decreases in sizes of integrated circuits (IC) and circuit components in semiconductor chips, there are a number of interconnect wiring challenges facing the technical community over the next few technology generations. Among these challenges include the electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects. However, both of these features of smaller ICs result in an undesirable increase in capacitance between conductive portions of the IC, which in turn, results in loss of speed of the IC and Increased cross-talk
In addressing the above problems, prior art has focused on replacing conventional SiO2 dielectric materials typically having a dielectric constant (k) of about 4.0. Lower dielectric constant materials have replaced the conventional materials, a d thereby have lowered the overall interconnect capacitance of the IC. One such avenue pursued to lower interconnect capacitance has been the use of low-k dielectrics. These low-k dielectrics tend to have a dielectric constant (k) of about 3.0 or less. The prior art is replete with various low-k dielectric materials and methods of forming the same over a substrate for lowering the interconnect capacitance.
However, as ICs have become smaller and faster, the need to reduce the interconnect capacitance even further has persisted. One technique introduced, in the art is to provide low-k dielectric materials with porosity for a further reduction in interconnect capacitance. By adding porosity to a low-k dielectric material, the dielectric constant (k) can be decreased down to about 2.0, or even less.
Generally, a porous low-k dielectric layer is formed on an Integrated circuit structure by depositing a low-k dielectric material in combination with an extractable material, such as a porogen. During such fabrication process, the porogen is removed from the low-k dielectric material, thereby leaving a number of pores having a variety of shapes and sizes residing throughout the low-k dielectric layer. Numerous porous low-k dielectric materials, and methods of making the same, exist in the art.
Once the porous low-k dielectric layers are fabricated, IC fabrication continues by patterning and etching openings into the porous low-k dielectric layers. These openings commonly include damascene and/or dual damascene vias and/or trenches that are subsequently filled with metallization, such as copper fill. However, as a result of etching openings into the porous low-k dielectric layer, one or more of the pores residing throughout the porous layer are exposed. These exposed pores may reside on a planar surface of the porous layer and/or within the via/trench openings. Exposed pores are undesirable as they can create voids on the planar surface and in the via/trench openings, which when subsequently filled with metallization, can degrade the deposited metallurgy and even lead to shorting between adjacent metal-filled vias and trenches.
To overcome these problems associated with exposed pores, prior art has focused on sealing, blocking or closing exposed pores of a porous low-k dielectric layer. Conventional approaches include depositing a liner layer over exposed planar surfaces of the porous low-k dielectric layer and/or within via/trench openings to close exposed pores therein. For example, prior art is directed to forming a barrier liner layer, such as tantalum metal, over exposed surfaces of the via/trench openings to both cover these surfaces and close any exposed pores within such openings. Conductive metallurgy, such as copper, subsequently fills the remaining empty portions of the via/trench openings.
However, providing a barrier liner layer over exposed surfaces, and hence any exposed pores, within the via/trench openings is often inadequate. For instance, the deposited barrier layer may not completely fill the exposed pores within the via/trench openings, such that when metallurgy is subsequently deposited, it too may not completely fill remaining portions of the exposed pores. This results in voids in the deposited metallurgy, which leads to high resistance of metallurgy at the location of such void(s) and degradation of the deposited metallurgy.
Alternatively, or in addition to the above, wherein the barrier liner layer does not completely cover surfaces within the void, i.e., a portion of the porous low-k dielectric layer is exposed in the exposed pore, deposited metallurgy may directly contact such porous low-k dielectric layer. Direct contact between the porous low-k dielectric layer and the deposited metallurgy results in the diffusion of metal atoms, e.g., copper atoms, into the porous dielectric layer. This is undesirable as it increases the low dielectric constant (k) of the porous low-k dielectric layer, as well as degrades the dielectric properties thereof. Another disadvantage of coating via/trench opening surfaces with a deposited metal liner is that the metal material typically has a higher resistance and lower conductivity in comparison to the subsequently deposited metallurgy. This may provide a damascene wire having unacceptably high resistance that adversely affects performance of the IC.
As IC dimensions continue to shrink with future generations of semiconductor technology, these conventional techniques of depositing a barrier or liner layer to fill exposed pores in a porous dielectric layer are becoming increasingly inefficient. This is especially the case wherein exposed pores of the porous dielectric layer reside within via and/or trench openings. As IC dimensions scale down, the dimensions of these via/trench openings also decrease. In so doing, in the process of depositing a barrier liner layer to close exposed pores within via/trench openings, this deposited barrier liner layer undesirably occupies valuable space within these smaller openings. In turn, an insufficient amount of metallurgy will be subsequently depositing into the remaining openings resulting in an undesirably increase in wire resistance.
In attempting to overcome the problems associated with exposed pores, prior art has also focused on depositing inorganic dielectric layers to close these exposed pores. For instance, one such approach includes depositing a plasma enhanced chemical vapor deposition layer (PECVD), such as a PECVD SiO2 layer, which conformally coats exposed surfaces of the porous dielectric layer, including any exposed surfaces with via/trench openings. Typically, the deposition of the Inorganic layer continues until the exposed pores are pinched-off and closed such that a conformal PECVD layer has been deposited within via/trench openings coating exposed surfaces therein.
However, this approach of depositing inorganic dielectric layers also suffers from the problems associated with deposition of barrier liner layers. That is, they add additional thickness or material into the continually decreasing sized openings in the porous dielectric layers. Also, like that of the deposited metal liner layers, deposited inorganic layers detrimentally decrease the size of the already reduced via/trench openings even further, such that insufficient amounts of metallurgy is deposited, resulting in an increase in the wire resistant of the resultant IC. Another problem with these depositing inorganic dielectric layers is that they generally have a higher dielectric constant than the porous low-k dielectric layer to which it makes contact, thereby unacceptably increasing the overall capacitance of the IC.
Accordingly, as IC dimensions continue to scale down in size with future generations of semiconductor-technology, improved structures and methods are needed to close exposed pores in a porous low-k dielectric layer, whether such exposed pores reside at exposed surface areas of the IC or within via and/or trench openings in the porous low-k dielectric layer.